alpaka
Abstraction Library for Parallel Kernel Acceleration
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syclConfig.hpp
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1/* Copyright 2023 Andrea Bocci, Aurora Perego, René Widera
2 * SPDX-License-Identifier: MPL-2.0
3 */
4
5#include "alpaka/core/config.hpp"
6
7#if ALPAKA_LANG_SYCL
8
9# if defined(__SYCL_DEVICE_ONLY__)
10
11// defines can be taken from
12// https://github.com/llvm/llvm-project/blob/3cfe6aa46e06a8caa3f07057838d31c6ce840076/clang/include/clang/Basic/OffloadArch.h#L18-L28
13
14# if /* Broadwell Intel graphics architecture */ \
15 (defined(__SYCL_TARGET_INTEL_GPU_BDW__) && __SYCL_TARGET_INTEL_GPU_BDW__) \
16 || /* Skylake Intel graphics architecture */ \
17 (defined(__SYCL_TARGET_INTEL_GPU_SKL__) && __SYCL_TARGET_INTEL_GPU_SKL__) \
18 || /* Kaby Lake Intel graphics architecture */ \
19 (defined(__SYCL_TARGET_INTEL_GPU_KBL__) && __SYCL_TARGET_INTEL_GPU_KBL__) \
20 || /* Coffee Lake Intel graphics architecture */ \
21 (defined(__SYCL_TARGET_INTEL_GPU_CFL__) && __SYCL_TARGET_INTEL_GPU_CFL__) \
22 || /* Apollo Lake Intel graphics architecture */ \
23 (defined(__SYCL_TARGET_INTEL_GPU_APL__) && __SYCL_TARGET_INTEL_GPU_APL__) \
24 || /* Gemini Lake Intel graphics architecture */ \
25 (defined(__SYCL_TARGET_INTEL_GPU_GLK__) && __SYCL_TARGET_INTEL_GPU_GLK__) \
26 || /* Whiskey Lake Intel graphics architecture */ \
27 (defined(__SYCL_TARGET_INTEL_GPU_WHL__) && __SYCL_TARGET_INTEL_GPU_WHL__) \
28 || /* Amber Lake Intel graphics architecture */ \
29 (defined(__SYCL_TARGET_INTEL_GPU_AML__) && __SYCL_TARGET_INTEL_GPU_AML__) \
30 || /* Comet Lake Intel graphics architecture */ \
31 (defined(__SYCL_TARGET_INTEL_GPU_CML__) && __SYCL_TARGET_INTEL_GPU_CML__) \
32 || /* Ice Lake Intel graphics architecture */ \
33 (defined(__SYCL_TARGET_INTEL_GPU_ICLLP__) && __SYCL_TARGET_INTEL_GPU_ICLLP__) \
34 || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \
35 (defined(__SYCL_TARGET_INTEL_GPU_EHL__) && __SYCL_TARGET_INTEL_GPU_EHL__) \
36 || /* Tiger Lake Intel graphics architecture */ \
37 (defined(__SYCL_TARGET_INTEL_GPU_TGLLP__) && __SYCL_TARGET_INTEL_GPU_TGLLP__) \
38 || /* Rocket Lake Intel graphics architecture */ \
39 (defined(__SYCL_TARGET_INTEL_GPU_RKL__) && __SYCL_TARGET_INTEL_GPU_RKL__) \
40 || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \
41 (defined(__SYCL_TARGET_INTEL_GPU_ADL_S__) && __SYCL_TARGET_INTEL_GPU_ADL_S__) \
42 || /* Alder Lake P Intel graphics architecture */ \
43 (defined(__SYCL_TARGET_INTEL_GPU_ADL_P__) && __SYCL_TARGET_INTEL_GPU_ADL_P__) \
44 || /* Alder Lake N Intel graphics architecture */ \
45 (defined(__SYCL_TARGET_INTEL_GPU_ADL_N__) && __SYCL_TARGET_INTEL_GPU_ADL_N__) \
46 || /* DG1 Intel graphics architecture */ \
47 (defined(__SYCL_TARGET_INTEL_GPU_DG1__) && __SYCL_TARGET_INTEL_GPU_DG1__) \
48 || /* Alchemist G10 Intel graphics architecture */ \
49 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G10__) && __SYCL_TARGET_INTEL_GPU_ACM_G10__) \
50 || /* Alchemist G11 Intel graphics architecture */ \
51 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G11__) && __SYCL_TARGET_INTEL_GPU_ACM_G11__) \
52 || /* Alchemist G12 Intel graphics architecture */ \
53 (defined(__SYCL_TARGET_INTEL_GPU_ACM_G12__) && __SYCL_TARGET_INTEL_GPU_ACM_G12__) \
54 || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \
55 (defined(__SYCL_TARGET_INTEL_GPU_MTL_U__) && __SYCL_TARGET_INTEL_GPU_MTL_U__) \
56 || /* Meteor Lake H Intel graphics architecture */ \
57 (defined(__SYCL_TARGET_INTEL_GPU_MTL_H__) && __SYCL_TARGET_INTEL_GPU_MTL_H__) \
58 || /* Arrow Lake H Intel graphics architecture */ \
59 (defined(__SYCL_TARGET_INTEL_GPU_ARL_H__) && __SYCL_TARGET_INTEL_GPU_ARL_H__) \
60 || /* Battlemage G21 Intel graphics architecture */ \
61 (defined(__SYCL_TARGET_INTEL_GPU_BMG_G21__) && __SYCL_TARGET_INTEL_GPU_BMG_G21__) \
62 || /* Lunar Lake Intel graphics architecture */ \
63 (defined(__SYCL_TARGET_INTEL_GPU_LNL_M__) && __SYCL_TARGET_INTEL_GPU_LNL_M__)
64
65# define ALPAKA_SYCL_SUBGROUP_SIZE (8 | 16 | 32)
66
67# elif /* Ponte Vecchio Intel graphics architecture */ \
68 (defined(__SYCL_TARGET_INTEL_GPU_PVC__) && __SYCL_TARGET_INTEL_GPU_PVC__) \
69 || /* Ponte Vecchio VG Intel graphics architecture */ \
70 (defined(__SYCL_TARGET_INTEL_GPU_PVC_VG__) && __SYCL_TARGET_INTEL_GPU_PVC_VG__)
71
72# define ALPAKA_SYCL_SUBGROUP_SIZE (16 | 32)
73
74# elif(/* generate code ahead of time for x86_64 CPUs */ \
75 defined(__SYCL_TARGET_INTEL_X86_64__) && __SYCL_TARGET_INTEL_X86_64__)
76// @attention ony CPU side detachment of SYCL kernel we limit the CPU currently to max warp group size of 32, therefore
77// 64 is removed from this list
78# define ALPAKA_SYCL_SUBGROUP_SIZE (1 | 2 | 4 | 8 | 16 | 32)
79
80# elif /* NVIDIA Maxwell architecture (compute capability 5.0) */ \
81 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_50__) && __SYCL_TARGET_NVIDIA_GPU_SM_50__) \
82 || /* NVIDIA Maxwell architecture (compute capability 5.2) */ \
83 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_52__) && __SYCL_TARGET_NVIDIA_GPU_SM_52__) \
84 || /* NVIDIA Jetson TX1 / Nano (compute capability 5.3) */ \
85 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_53__) && __SYCL_TARGET_NVIDIA_GPU_SM_53__) \
86 || /* NVIDIA Pascal architecture (compute capability 6.0) */ \
87 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_60__) && __SYCL_TARGET_NVIDIA_GPU_SM_60__) \
88 || /* NVIDIA Pascal architecture (compute capability 6.1) */ \
89 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_61__) && __SYCL_TARGET_NVIDIA_GPU_SM_61__) \
90 || /* NVIDIA Jetson TX2 (compute capability 6.2) */ \
91 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_62__) && __SYCL_TARGET_NVIDIA_GPU_SM_62__) \
92 || /* NVIDIA Volta architecture (compute capability 7.0) */ \
93 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_70__) && __SYCL_TARGET_NVIDIA_GPU_SM_70__) \
94 || /* NVIDIA Jetson AGX (compute capability 7.2) */ \
95 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_72__) && __SYCL_TARGET_NVIDIA_GPU_SM_72__) \
96 || /* NVIDIA Turing architecture (compute capability 7.5) */ \
97 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_75__) && __SYCL_TARGET_NVIDIA_GPU_SM_75__) \
98 || /* NVIDIA Ampere architecture (compute capability 8.0) */ \
99 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_80__) && __SYCL_TARGET_NVIDIA_GPU_SM_80__) \
100 || /* NVIDIA Ampere architecture (compute capability 8.6) */ \
101 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_86__) && __SYCL_TARGET_NVIDIA_GPU_SM_86__) \
102 || /* NVIDIA Jetson/Drive AGX Orin (compute capability 8.7) */ \
103 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_87__) && __SYCL_TARGET_NVIDIA_GPU_SM_87__) \
104 || /* NVIDIA Ada Lovelace arch. (compute capability 8.9) */ \
105 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_89__) && __SYCL_TARGET_NVIDIA_GPU_SM_89__) \
106 || /* NVIDIA Hopper architecture (compute capability 9.0) */ \
107 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90__) && __SYCL_TARGET_NVIDIA_GPU_SM_90__) \
108 || /*NVIDIA Hopper architecture variant(compute capability 9.0a) */ \
109 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_90a__) && __SYCL_TARGET_NVIDIA_GPU_SM_90a__) \
110 || /* NVIDIA Blackwell architecture (compute capability 10.0) */ \
111 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100__) && __SYCL_TARGET_NVIDIA_GPU_SM_100__) \
112 || /* NVIDIA Blackwell architecture variant (compute capability 10.0a) */ \
113 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_100a__) && __SYCL_TARGET_NVIDIA_GPU_SM_100a__) \
114 || /* NVIDIA Blackwell Next architecture (compute capability 10.1) */ \
115 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101__) && __SYCL_TARGET_NVIDIA_GPU_SM_101__) \
116 || /* NVIDIA Blackwell Next architecture variant (compute capability 10.1a) */ \
117 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_101a__) && __SYCL_TARGET_NVIDIA_GPU_SM_101a__) \
118 || /* NVIDIA Next-generation architecture (compute capability 10.3) */ \
119 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103__) && __SYCL_TARGET_NVIDIA_GPU_SM_103__) \
120 || /* NVIDIA Next-generation architecture variant (compute capability 10.3a) */ \
121 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_103a__) && __SYCL_TARGET_NVIDIA_GPU_SM_103a__) \
122 || /* NVIDIA Future architecture (compute capability 12.0) */ \
123 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120__) && __SYCL_TARGET_NVIDIA_GPU_SM_120__) \
124 || /* NVIDIA Future architecture variant (compute capability 12.0a) */ \
125 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_120a__) && __SYCL_TARGET_NVIDIA_GPU_SM_120a__) \
126 || /* NVIDIA Future architecture (compute capability 12.1) */ \
127 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121__) && __SYCL_TARGET_NVIDIA_GPU_SM_121__) \
128 || /* NVIDIA Future architecture variant (compute capability 12.1a) */ \
129 (defined(__SYCL_TARGET_NVIDIA_GPU_SM_121a__) && __SYCL_TARGET_NVIDIA_GPU_SM_121a__)
130
131# define ALPAKA_SYCL_SUBGROUP_SIZE (32) /* CUDA supports warp size 32 */
132
133# elif /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
134 (defined(__SYCL_TARGET_AMD_GPU_GFX700__) && __SYCL_TARGET_AMD_GPU_GFX700__) \
135 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
136 (defined(__SYCL_TARGET_AMD_GPU_GFX701__) && __SYCL_TARGET_AMD_GPU_GFX701__) \
137 || /* AMD GCN 2.0 Sea Islands architecture (gfx 7.0) */ \
138 (defined(__SYCL_TARGET_AMD_GPU_GFX702__) && __SYCL_TARGET_AMD_GPU_GFX702__) \
139 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
140 (defined(__SYCL_TARGET_AMD_GPU_GFX801__) && __SYCL_TARGET_AMD_GPU_GFX801__) \
141 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
142 (defined(__SYCL_TARGET_AMD_GPU_GFX802__) && __SYCL_TARGET_AMD_GPU_GFX802__) \
143 || /* AMD GCN 4.0 Arctic Islands architecture (gfx 8.0) */ \
144 (defined(__SYCL_TARGET_AMD_GPU_GFX803__) && __SYCL_TARGET_AMD_GPU_GFX803__) \
145 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.0) */ \
146 (defined(__SYCL_TARGET_AMD_GPU_GFX805__) && __SYCL_TARGET_AMD_GPU_GFX805__) \
147 || /* AMD GCN 3.0 Volcanic Islands architecture (gfx 8.1) */ \
148 (defined(__SYCL_TARGET_AMD_GPU_GFX810__) && __SYCL_TARGET_AMD_GPU_GFX810__) \
149 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
150 (defined(__SYCL_TARGET_AMD_GPU_GFX900__) && __SYCL_TARGET_AMD_GPU_GFX900__) \
151 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
152 (defined(__SYCL_TARGET_AMD_GPU_GFX902__) && __SYCL_TARGET_AMD_GPU_GFX902__) \
153 || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
154 (defined(__SYCL_TARGET_AMD_GPU_GFX904__) && __SYCL_TARGET_AMD_GPU_GFX904__) \
155 || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \
156 (defined(__SYCL_TARGET_AMD_GPU_GFX906__) && __SYCL_TARGET_AMD_GPU_GFX906__) \
157 || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \
158 (defined(__SYCL_TARGET_AMD_GPU_GFX908__) && __SYCL_TARGET_AMD_GPU_GFX908__) \
159 || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \
160 (defined(__SYCL_TARGET_AMD_GPU_GFX909__) && __SYCL_TARGET_AMD_GPU_GFX909__) \
161 || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \
162 (defined(__SYCL_TARGET_AMD_GPU_GFX90A__) && __SYCL_TARGET_AMD_GPU_GFX90A__) \
163 || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \
164 (defined(__SYCL_TARGET_AMD_GPU_GFX90C__) && __SYCL_TARGET_AMD_GPU_GFX90C__) \
165 || /* AMD CDNA 3.x generic architecture (gfx 9.4) */ \
166 (defined(__SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_4_GENERIC__) \
167 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
168 (defined(__SYCL_TARGET_AMD_GPU_GFX940__) && __SYCL_TARGET_AMD_GPU_GFX940__) \
169 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
170 (defined(__SYCL_TARGET_AMD_GPU_GFX941__) && __SYCL_TARGET_AMD_GPU_GFX941__) \
171 || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
172 (defined(__SYCL_TARGET_AMD_GPU_GFX942__) && __SYCL_TARGET_AMD_GPU_GFX942__) \
173 || /* AMD CDNA 3.5 derivative architecture (gfx 9.5) */ \
174 (defined(__SYCL_TARGET_AMD_GPU_GFX950__) && __SYCL_TARGET_AMD_GPU_GFX950__) \
175 || /* AMD GCN 5.x generic architecture (gfx 9.x) */ \
176 (defined(__SYCL_TARGET_AMD_GPU_GFX9_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX9_GENERIC__)
177
178# define ALPAKA_SYCL_SUBGROUP_SIZE (64) /* up to gfx9, HIP supports wavefront size 64 */
179
180# elif /* AMD RDNA 1.0 Navi 10 architecture (gfx 10.1) */ \
181 (defined(__SYCL_TARGET_AMD_GPU_GFX1010__) && __SYCL_TARGET_AMD_GPU_GFX1010__) \
182 || /* AMD RDNA 1.0 Navi 12 architecture (gfx 10.1) */ \
183 (defined(__SYCL_TARGET_AMD_GPU_GFX1011__) && __SYCL_TARGET_AMD_GPU_GFX1011__) \
184 || /* AMD RDNA 1.0 Navi 14 architecture (gfx 10.1) */ \
185 (defined(__SYCL_TARGET_AMD_GPU_GFX1012__) && __SYCL_TARGET_AMD_GPU_GFX1012__) \
186 || /* AMD RDNA 2.0 Oberon architecture (gfx 10.1) */ \
187 (defined(__SYCL_TARGET_AMD_GPU_GFX1013__) && __SYCL_TARGET_AMD_GPU_GFX1013__) \
188 || /* AMD RDNA 1.x generic architecture (gfx 10.1) */ \
189 (defined(__SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_1_GENERIC__) \
190 || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \
191 (defined(__SYCL_TARGET_AMD_GPU_GFX1030__) && __SYCL_TARGET_AMD_GPU_GFX1030__) \
192 || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \
193 (defined(__SYCL_TARGET_AMD_GPU_GFX1031__) && __SYCL_TARGET_AMD_GPU_GFX1031__) \
194 || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \
195 (defined(__SYCL_TARGET_AMD_GPU_GFX1032__) && __SYCL_TARGET_AMD_GPU_GFX1032__) \
196 || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \
197 (defined(__SYCL_TARGET_AMD_GPU_GFX1033__) && __SYCL_TARGET_AMD_GPU_GFX1033__) \
198 || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
199 (defined(__SYCL_TARGET_AMD_GPU_GFX1034__) && __SYCL_TARGET_AMD_GPU_GFX1034__) \
200 || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \
201 (defined(__SYCL_TARGET_AMD_GPU_GFX1035__) && __SYCL_TARGET_AMD_GPU_GFX1035__) \
202 || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \
203 (defined(__SYCL_TARGET_AMD_GPU_GFX1036__) && __SYCL_TARGET_AMD_GPU_GFX1036__) \
204 || /* AMD RDNA 2.x generic architecture (gfx 10.3) */ \
205 (defined(__SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX10_3_GENERIC__) \
206 || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \
207 (defined(__SYCL_TARGET_AMD_GPU_GFX1100__) && __SYCL_TARGET_AMD_GPU_GFX1100__) \
208 || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \
209 (defined(__SYCL_TARGET_AMD_GPU_GFX1101__) && __SYCL_TARGET_AMD_GPU_GFX1101__) \
210 || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
211 (defined(__SYCL_TARGET_AMD_GPU_GFX1102__) && __SYCL_TARGET_AMD_GPU_GFX1102__) \
212 || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \
213 (defined(__SYCL_TARGET_AMD_GPU_GFX1103__) && __SYCL_TARGET_AMD_GPU_GFX1103__) \
214 || /* AMD RDNA 3.x generic architecture (gfx 11.x) */ \
215 (defined(__SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX11_GENERIC__) \
216 || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \
217 (defined(__SYCL_TARGET_AMD_GPU_GFX1150__) && __SYCL_TARGET_AMD_GPU_GFX1150__) \
218 || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \
219 (defined(__SYCL_TARGET_AMD_GPU_GFX1151__) && __SYCL_TARGET_AMD_GPU_GFX1151__) \
220 || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \
221 (defined(__SYCL_TARGET_AMD_GPU_GFX1200__) && __SYCL_TARGET_AMD_GPU_GFX1200__) \
222 || /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ \
223 (defined(__SYCL_TARGET_AMD_GPU_GFX1201__) && __SYCL_TARGET_AMD_GPU_GFX1201__) \
224 || /* AMD RDNA 4.x generic architecture (gfx 12.x) */ \
225 (defined(__SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) && __SYCL_TARGET_AMD_GPU_GFX12_GENERIC__) \
226 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
227 (defined(__SYCL_TARGET_AMD_GPU_GFX1250__) && __SYCL_TARGET_AMD_GPU_GFX1250__) \
228 || /* AMD RDNA 4.5 derivative architecture (gfx 12.5) */ \
229 (defined(__SYCL_TARGET_AMD_GPU_GFX1251__) && __SYCL_TARGET_AMD_GPU_GFX1251__)
230
231# define ALPAKA_SYCL_SUBGROUP_SIZE (32) /* starting from gfx10, HIP supports wavefront size 32 */
232
233# else // __SYCL_TARGET_*
234
235// if we do not compile ahead of time for a device and use e.g. -fsycl-targets=spir64 we need to accept all possible
236// variants
237# define ALPAKA_SYCL_SUBGROUP_SIZE (0xFFFF'FFFF) /* unknown target */
238
239# endif // __SYCL_TARGET_*
240
241# else
242
243// ony the host side we need to allow all possible variants of a subgroup size else kernel will not be build
244# define ALPAKA_SYCL_SUBGROUP_SIZE (0xFFFF'FFFF) /* host compilation */
245
246# endif // __SYCL_DEVICE_ONLY__
247
248#endif
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